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AS4C32M16D1A - c&i 0 rev. 1.0 mar. /201 5 revision history revision details date rev 1.0 preliminary datasheet march 201 5 alliance memory inc . 511 taylor way, san carlos, ca 94070 tel : (650) 610 - 6800 fax : (650) 620 - 9211 alliance memory inc. reserves the right to change products or specification without notice.
AS4C32M16D1A - c&i 1 rev. 1.0 mar. /201 5 32 m x 16 bit ddr synchronous dram (sdram) adv a nced ( rev. 1 .0 , mar . / 20 1 5 ) features ? fast clock rate: 200mhz ? differential clock ck & ? bi - directional dqs ? dll enable/disable by emrs ? fully synchronous operation ? internal pipeline architecture ? four internal banks, 8 m x 16 - bit for each bank ? programmable mode and extended mode registers - cas latency: 2, 2.5, 3 - burst length: 2, 4, 8 - burst type: sequential & interleaved ? individual byte write mask control ? dm write latency = 0 ? auto refresh and self refresh ? 8192 refresh cycles / 64 ms ? precharge & active power down ? power supplies: vdd & vddq = 2.5v 0.2v ? operating temperature: - commercial ( 0 c ~ 70 c ) - industrial ( - 4 0 c ~ 85 c ) ? interface: sstl_2 i/o interface ? package: 66 pin tsop ii, 0.65mm pin pitch - p b and halogen free ck
AS4C32M16D1A - c&i 2 rev. 1. 0 mar . / 20 1 5 overview the 512mb ddr sdram is a high - speed cmos double data rate synchronous dram containing 512 mbits. it is internally configured as a quad 8 m x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, ck). data outputs occur at both r ising edges of ck and . read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registrati on of a bankactivate command which is then followed by a read or write command. the device provides programmable read or write burst lengths of 2, 4, or 8. an auto precharge function may be enabled to provide a self - timed row precharge that is initiated at the end of the burst sequence. the refresh functions, either auto or self refresh are easy to use. in addition, 512mb ddr features programmable dll option. by having a programmable mode register and extended mode register, the system can choose the most s uitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications. table 1 . ordering information part number clock frequency data rate package t emperature t emp range AS4C32M16D1A - 5 tcn 200 mhz 400mbps/pin 66 pin tsop ii c ommercial 0 ~ 70 AS4C32M16D1A - 5 t i n 200 mhz 400mbps/pin 66 pin tsop ii i ndustrial - 40 ~ 8 5 t : indicates tsop ii package c: commercial i: industrial n : ind icates pb free and halogen free ck
AS4C32M16D1A - c&i 3 rev. 1. 0 mar . / 20 1 5 f igure 1. pin assignment ( top view) v s s q 1 6 6 v d d v s s 2 6 5 d q 0 d q 1 5 3 6 4 v d d q v s s q 4 6 3 d q 1 d q 1 4 5 6 2 d q 2 d q 1 3 6 6 1 v s s q v d d q 7 6 0 d q 3 d q 1 2 8 5 9 d q 4 d q 1 1 9 5 8 v d d q v s s q 1 0 5 7 d q 5 d q 1 0 1 1 5 6 d q 6 d q 9 1 2 5 5 v s s q v d d q 1 3 5 4 d q 7 d q 8 1 4 5 3 n c n c 1 5 5 2 v d d q 1 6 5 1 l d q s u d q s 1 8 4 9 v d d v r e f 1 9 4 8 n c v s s 2 0 4 7 l d m u d m 2 2 4 5 c a s c k 2 3 4 4 r a s c k e 2 4 4 3 c s n c 2 5 4 2 n c a 1 2 2 6 4 1 b a 0 a 1 1 2 7 4 0 b a 1 a 9 2 8 3 9 a 1 0 / a p a 8 2 9 3 8 a 0 a 7 1 7 5 0 n c n c 2 1 4 6 w e c k 3 1 3 6 a 2 a 5 3 2 3 5 a 3 a 4 3 3 3 4 v d d v s s 3 0 3 7 a 1 a 6
AS4C32M16D1A - c&i 4 rev. 1. 0 mar . / 20 1 5 f igure 2. block diagram c k c k e c s r a s c a s w e d l l c l o c k b u f f e r c o m m a n d d e c o d e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r a d d r e s s b u f f e r r e f r e s h c o u n t e r 8 m x 1 6 c e l l a r r a y ( b a n k # 0 ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # 1 ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # 2 ) r o w d e c o d e r 8 m x 1 6 c e l l a r r a y ( b a n k # 3 ) r o w d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r m o d e r e g i s t e r a 1 0 / a p a 9 a 1 1 a 1 2 b a 0 b a 1 ~ a 0 c k d a t a s t r o b e b u f f e r l d q s u d q s d q b u f f e r l d m u d m d q 1 5 d q 0 ~
AS4C32M16D1A - c&i 1 rev. 1. 0 mar . / 20 1 5 pin descriptions table 2 . pin details symbol type description ck, input differential clock: ck and are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of . input and output data is referenced to the crossing of ck and (both directions of the crossing) cke input clock enable: cke activates (high) and deactivates ( low) the ck signal. if cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. b a 0, b a 1 input bank activate : b a 0 and b a 1 define to which bank the bankactiva te, read, write, or bankprecharge command is being applied. a0 - a1 2 input address inputs: a0 - a1 2 are sampled during the bankactivate command (row address a0 - a1 2 ) and read/write command (column address a0 - a 9 with a10 defining aut o precharge). input chip select: enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when is sampled high. provides for external bank selection on systems with multiple banks. it is considered part of the command code. input row address strobe: the signal defines the operation commands in conjunction with the and signals and is latched at the positive edges of ck. when and are asserted "low" and is asserted "high," either the bankactivate command or the precharge command is selected by the signal. when the is asserted "high," the bankactivate command is selected and the bank designated by b a is turned on to the active state. when the is asserted "low," the precharge command is selected and the bank designated by b a is switched to the idle state after the precharge operation. input column address strobe: the signal defines the operation commands in conjunction with the and signals and is latched at the positive edges of ck. when is held "high" and is asserted "low," the column access is started by asserting "low." then, the read or write command is selected by asserting "high" or low . input write enable: the signal defines the operation commands in conjunction with the and signals and is latched at the positive edges of ck. the input is used to select the bankactivate or precharge command and read or write command. ldqs, udqs input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for dat a and dqm. ldqs is for dq0~7, udqs is for dq8~15. ldm, udm input data input mask: input data is masked when dm is sampled high during a write cycle. ldm masks dq0 - dq7, udm masks dq8 - dq15. dq0 - dq15 input / output data i/o: the dq0 - dq15 input and output data are synchronized with positive and negative edges of ldqs and udqs. the i/os are byte - maskable during writes . v dd supply power supply: 2.5v 0.2v . ck cs cs ras ras cas we ras cs cas we we we cas ras we ras cs cas we we ras cas we
AS4C32M16D1A - c&i 2 rev. 1. 0 mar . / 20 1 5 v ss supply ground v ddq supply dq power: 2.5v 0.2v . provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: these pins should be left unconnected.
AS4C32M16D1A - c&i 3 rev. 1. 0 mar . / 20 1 5 ope ration mode table 3 shows the truth table for the operation commands. table 3 . truth table (note (1), (2 )) command state cke n - 1 cke n dm b a 0,1 a 10 a 0 - 9, 11 - 1 2 bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x x v l column address (a0 ~ a 9 ) l h l l write and autoprecharge active (3) h x x v h l h l l read active (3) h x x v l column address (a0 ~ a 9 ) l h l h read and autoprecharge active (3) h x x v h l h l h mode register set idle h x x op code l l l l extended mrs idle h x x op code l l l l no - operation any h x x x x x l h h h burst st op active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h precharge power down mode entry idle h l x x x x h x x x l h h h precharge power down mode exit any l h x x x x h x x x (powerdown) l h h h active power down mode entry active h l x x x x h x x x l v v v active power down mode exit any l h x x x x h x x x (powerdown) l h h h data in put mask disable active h x l x x x x x x x data input mask enable(5) active h x h x x x x x x x note: 1. v=valid data, x=don't care, l=low level, h=high level 2. cke n signal is input level when commands are provide d. cke n - 1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by b a signal. 4. device state is 2, 4, and 8 burst operation. 5. ldm and udm can be enable d respectively. cs ras cas we
AS4C32M16D1A - c&i 4 rev. 1. 0 mar . / 20 1 5 mode register set (mr s) the mode register stores the data for controlling various operating modes of a ddr sdram. it programs cas latency, burst type, and burst length to make the ddr sdram useful for a variety of applications. the default value of the mode register is not def ined; therefore the mode register must be written by the user. values stored in the register will be retained until the register is reprogrammed. the mode register is written by asserting low on , , , , ba1 and ba0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and cke should be high). the state of address pins a0~a1 2 and ba0, ba1 in the same cycle in which , , and are asserted low is written into the mode register. a minimum of two clock cycles, tmrd, are required to complete the write operation in the mode register. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, burst type uses a3, and cas latency (read latency from column address) uses a4~a6. a logic 0 should be programmed to all the undefined addresses to ensure future compatibility. reserved states should not be used to avoid unknown device operation or incompatibility with future versions. refer to the table for specific codes for various burst lengths, burst types and cas l atencies . table 4. mode register bitmap b a1 b a0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 rfu must be set to 0 0 normal mode 0 0 0 reserved 0 sequential 0 0 0 reserved 1 0 dll reset 0 0 1 reserved 1 interleave 0 0 1 2 x 1 test mode 0 1 0 2 0 1 0 4 0 1 1 3 0 1 1 8 ba0 mode 1 0 0 reserved 1 0 0 r eserved 0 mrs 1 0 1 reserved 1 0 1 reserved 1 emrs 1 1 0 2.5 1 1 0 reserved 1 1 1 reserved 1 1 1 reserved ? this field specifies the data length of column access using the a2~ a0 pins and selects the burst length to be 2, 4, 8. table 5 . burst length a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved cas cs ras we
AS4C32M16D1A - c&i 5 rev. 1. 0 mar . / 20 1 5 ? addressing mo de select field (a3) the addressing mode can be one of two modes, either interleave mode or sequential mode. both sequential mode and interleave mode support burst length of 2, 4 and 8. table 6 . addressing mode a3 addressing mode 0 sequential 1 interlea ve ? table 7 . burst address ordering burst length start address sequential interleave a2 a1 a0 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3 , 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3 , 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 ? cac (min) ? cas latency x t ck table 8 . cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 clocks 1 1 1 reserved ? table 9 . test mode a8 a7 test mode 0 0 normal mode 1 0 dll reset
AS4C32M16D1A - c&i 6 rev. 1. 0 mar . / 20 1 5 ? ( b a 0, b a 1) table 10 . mrs/emrs b a 1 b a 0 a 12 ~ a0 rfu 0 mrs cycle rfu 1 extended functions (emrs) extended mode register set (emrs) the extended mode register set stores the data for enab ling or disabling dll and selecting output driver strength. the default value of the extended mode register is not defined, therefore must be written after power up for proper oper ation. the extened mode register is written by asserting low on , , , , ba1 and ba0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and cke should be high) . the stat e of a0 ~ a1 2, b a 0 and b a 1 is written in the mode register in the same cycle as , , , and going low . the ddr sdram should be in a ll bank precharge wi th cke already high prior to writing into the extended mode register. a1 is used for setting driver strength to normal, or weak. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on b a 0 is used for emrs. refer to the table for specific codes. table 11. extended mode r egister bitmap b a1 b a0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 rfu must be set to enable 1 emrs 0 1 weak 1 disable 1 0 rfu reserved for future 1 1 matched impedance output driver matches impedance cs ras cas we cas cs ras we
AS4C32M16D1A - c&i 7 rev. 1. 0 mar . / 20 1 5 table 1 2 . absolute maximum rating symbol item values unit v in , v out input, output voltage - 0. 5 ~ v dd q + 0. 5 v v dd , v ddq power supply voltage - 1~3.6 v t a ambient temperature commercial 0~ 70 c industrial - 4 0~ 85 c t stg storage temperature - 5 5~150 c t solder solder ing temperature 2 60 c p d power dissipation 1 w i o s short circuit output current 50 ma note 1 : stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. note2 : these voltages are re lative to vss table 1 3 . recommended d.c. operating conditions symbol parameter min. max. unit note v dd power supply voltage 2.3 2.7 v v ddq power supply voltage (for i/o buffer) 2.3 2.7 v v ref input reference voltage 0.49*v ddq 0.51* v ddq v v ih (dc ) input high voltage (dc) v ref + 0.15 v ddq + 0.3 v v il (dc) input low voltage (dc) - 0.3 v ref C 0.15 v v tt termination voltage v ref - 0.04 v ref + 0.04 v v in (dc) input voltage level, ck and inputs - 0.3 v ddq + 0.3 v v id (dc ) input different voltage, ck and inputs 0.36 v ddq + 0.6 v i i input leakage current - 2 2 ? a i oz output leakage current - 5 5 ? a i oh output high current - 16.2 - ma v oh = 1.95v i ol output low current 16.2 - ma v ol = 0.35v note : all voltages are referenced to v ss . table 14. capacitan ce (v dd = 2. 5 v, f = 1mhz, t a = 25 ? symbol parameter min. max. unit c in 1 input capacitance (ck, ) 2 3 pf c in 2 input capacitance ( all other input - only pins ) 2 3 pf c i/o dq, dqs , dm input/output capacitance 4 5 pf note: these parameters are guaranteed by design, periodically sampled and are not 100% tested ck
AS4C32M16D1A - c&i 8 rev. 1. 0 mar . / 20 1 5 table 15. d.c. characteristics (v dd = 2.5 v ? a = - 40 ~ 85 ? parameter & test condition symbol - 5 unit note max . operating current: one bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. idd0 80 ma operating current : one bank; bl=4; reads - refer to the following page for detailed test conditions idd1 90 ma precharge power - down standby current: all banks idle; power - down mode; t ck =t ck (min); cke = low idd2p 5 ma p recharge floating standby current: cs = high ; all banks idl e; cke = high ; t ck =t ck (min) ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm idd2f 35 ma p recharge quiet standby current: cs =high ; all banks idle; cke =high ; t ck =t ck (min) address and other control inputs st able at ih (min) or il (max); v in = v ref for dq, dqs and dm idd2q 35 ma active power - down standby current : one bank active; power - down mode; cke=low; t ck =t ck (min) idd3p 20 ma active standby current : =high;cke=high; on e bank active ; t rc =t rc (max);t ck =t ck (min);address and control inputs changing once per clock cycle; dq,dqs,and dm inputs changing twice per clock cycle idd3n 65 ma operating current burst read : bl=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); lout=0ma;50% of data changing on every transfer idd4r 130 ma operating current burst write : bl=2; writes; continuous burst ;one bank active; a ddress and control inputs changing once per clock cycle; t ck =t ck (min); dq,dqs,and dm changing twice per clock cycle; 50% of data changing on every transfer idd4w 130 ma auto refresh current : t rc =t rfc (min); t ck =t ck (min) idd5 140 ma self refresh current: self refresh mode ; cke Q ck =t ck (min) idd6 6 ma 1 burst operating current 4 bank operation: four bank interleaving reads; bl=4;with auto precharge; t rc =t rc (min); t ck =t ck (min); address and control inputs chang e only during active, read , or write command idd7 210 ma cs
AS4C32M16D1A - c&i 9 rev. 1. 0 mar . / 20 1 5 table 1 6 . electrical characteristics and recommended a.c.operating c ondition (v dd = 2.5v 0.2v , t a = - 40 ~ 85 ? symbol parameter - 5 un it note min. max. t ck clock cycle time cl = 2 7.5 1 2 ns cl = 2.5 6 1 2 ns cl = 3 5 12 ns t ch clock high level width 0.45 0.55 t ck t cl clock low level width 0.45 0.55 t ck t hp clock half period t clmin or t chmin - ns 2 t hz data - out - high im pedance time from ck, - 0.7 ns 3 t lz data - out - low impedance time from ck, - 0.7 0.7 ns 3 t dqsck dqs - out access time from ck, - 0. 6 0. 6 ns t ac output access time from ck, - 0.7 0.7 ns t dqsq dqs - dq skew - 0.4 ns t rpre read preamble 0.9 1.1 t ck t rpst read postamble 0.4 0.6 t ck t dqss ck to valid dqs - in 0. 72 1.2 5 t ck t wpres dqs - in setup time 0 - ns 4 t wpre dqs write preamble 0. 2 5 - t ck t wp st dqs write postamble 0.4 0.6 t ck 5 t dqsh dqs in high level pulse width 0.35 - t ck t dqsl dqs in low level pulse width 0.35 - t ck t is address and control input setup time 0. 7 - ns 6 t ih address and control input hold time 0. 7 - ns 6 t ds dq & dm setu p time to dqs 0.4 - ns t dh dq & dm hold time to dqs 0.4 - ns t qh dq/dqs output hold time from dqs t hp - t qhs - ns t rc row cycle time 55 - ns t rfc refresh row cycle time 7 0 - ns t ras row active time 40 7 0k ns t rcd active to read or write delay 1 5 - ns t rp row precharge time 15 - ns t rrd row active to row active delay 10 - ns t w r write recovery time 15 - ns t w tr internal write to read command delay 2 - t ck t mrd mode register set cycle time 10 - ns t ref i average periodic refresh interva l - 7.8 ? s 7 t xs rd self refresh exit to read command delay 200 - t ck t xs nr self refresh exit to non - read command delay 75 - ns t d al auto precharge write recovery + precharge time t wr +t rp - ns t dipw dq and dm input puls e width 1.75 - ns t ipw c o ntrol and ad dress input pulse width 2.2 - ns t qhs data hold skew factor - 0.5 ns t ds s dq s falling edge to ck setup time 0.2 - t ck t ds h dq s falling edge hold time from ck 0.2 - t ck ck
AS4C32M16D1A - c&i 10 rev. 1. 0 mar . / 20 1 5 table 1 7 . recommended a.c. operating conditions (v dd = 2.5v 0.2v , t a = - 4 0~ 85 ? symbol parameter min. max. unit v ih ( ac ) input high voltage ( a c) v ref + 0. 31 - v v il ( ac ) input low voltage ( a c) - v ref C id ( a c) input different voltage, ck and inputs 0.7 v ddq + 0.6 v v i x ( a c) input crossing point voltage, ck and inputs 0.5* v ddq - 0.2 0.5* v ddq +0.2 v note: 1) enables on - chip refresh and address counters. 2) min(t c l , t ch ) refers to ther smaller of the actual clock low time and actual clock high time as provided to the device. 3) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific vol tage level, but specify when the device output is no longer driving(hz), or begins driving(lz). 4) the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as m onotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high - z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 5) the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 6) for command/a ddress and ck & slew rate R 1.0v/ns. 7) a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 8 ) power - up sequence is described in note 1 0 9 ) a.c. test conditions tabl e 1 8 . sstl _2 interface reference level of output signals (v r ef ) 0.5 * v ddq output load reference to the test load input signal levels v ref +0 .3 1 v / v ref - 0.3 1 v input signals slew rate 1 v/ns reference level of input signals 0.5 * v ddq ck ck
AS4C32M16D1A - c&i 11 rev. 1. 0 mar . / 20 1 5 figure 3. sstl_2 a.c. test load 1 0 ) power up seque nce power up must be performed in the following sequence. 1) apply p ower to v dd before or at the same time as v ddq , v tt and v ref when all input signals are held "nop" state and maintain cke low. 2) start clock and maintain stable condition for minimum 20 0 ? s. 3) issue a nop command and keep cke high 4) issue a precharge all command. 5 ) issue emrs C enable dll. 6 ) issue mrs C reset dll. (an additional 200 clock cycles are required to lock the dll). 7 ) precharge all banks of the device. 8 ) issue t wo or more auto refresh commands. 9) issue mrs C with a8 to low to initialize the mode register. d q , d q s z 0 = 5 0 5 0 3 0 p f 0 . 5 * v d d q
AS4C32M16D1A - c&i 12 rev. 1. 0 mar . / 20 1 5 timing waveforms figure 4. activating a specific row in a specific bank c k c k c k e c s r a s c a s w e r a a d d r e s s b a b a 0 , 1 d o n t c a r e h i g h r a = r o w a d d r e s s b a = b a n k a d d r e s s
AS4C32M16D1A - c&i 13 rev. 1. 0 mar . / 20 1 5 figure 5. trcd and trrd definition figure 6. read command c k c k a d d r e s s b a 0 , b a 1 a c t n o p c o m m a n d n o p a c t n o p n o p r d / w r n o p r o w r o w c o l b a n k a b a n k b b a n k b t r r d t r c d d o n t c a r e c k c k c k e c s r a s c a s w e c a a 0 - a 9 a 1 0 d o n t c a r e h i g h e n a p d i s a p b a b a 0 , 1 c a = c o l u m n a d d r e s s b a = b a n k a d d r e s s e n a p = e n a b l e a u t o p r e c h a r g e d i s a p = d i s a b l e a u t o p r e c h a r g e
AS4C32M16D1A - c&i 14 rev. 1. 0 mar . / 20 1 5 fig ure 7. read burst required cas latencies (cl=2) read burst required cas latencies (cl=2.5) c k c k c o m m a n d r e a d n o p n o p n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q c l = 2 d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n b u r s t l e n g t h = 4 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d o n c k c k c o m m a n d r e a d n o p n o p n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n b u r s t l e n g t h = 4 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d o n
AS4C32M16D1A - c&i 15 rev. 1. 0 mar . / 20 1 5 read burst requir ed cas latencies (cl=3) d o n c k c k c o m m a n d r e a d n o p n o p n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n b u r s t l e n g t h = 4 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n
AS4C32M16D1A - c&i 16 rev. 1. 0 mar . / 20 1 5 figure 8 . consecutive read bursts required cas latencies (cl=2) c k c k c o m m a n d r e a d n o p r e a d n o p n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 d o n d o n t c a r e b a n k , c o l o d o o d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 o r 8 ( i f 4 , t h e b u r s t s a r e c o n c a t e n a t e d ; i f 8 , t h e s e c o n d b u r s t i n t e r r u p t s t h e f i r s t ) 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n 3 ( o r 7 ) s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o o r e a d c o m m a n d s s h o w n m u s t b e t o t h e s a m e d e v i c e
AS4C32M16D1A - c&i 17 rev. 1. 0 mar . / 20 1 5 consecutive read bursts required cas latencies (cl=2.5) d o o c k c k c o m m a n d r e a d n o p r e a d n o p n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e b a n k , c o l o d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 o r 8 ( i f 4 , t h e b u r s t s a r e c o n c a t e n a t e d ; i f 8 , t h e s e c o n d b u r s t i n t e r r u p t s t h e f i r s t ) 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n 3 ( o r 7 ) s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o o r e a d c o m m a n d s s h o w n m u s t b e t o t h e s a m e d e v i c e d o n
AS4C32M16D1A - c&i 18 rev. 1. 0 mar . / 20 1 5 consecutive read bursts required cas latencies (cl= 3 ) d o o c k c k c o m m a n d r e a d n o p r e a d n o p n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e b a n k , c o l o d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 o r 8 ( i f 4 , t h e b u r s t s a r e c o n c a t e n a t e d ; i f 8 , t h e s e c o n d b u r s t i n t e r r u p t s t h e f i r s t ) 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n 3 ( o r 7 ) s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o o r e a d c o m m a n d s s h o w n m u s t b e t o t h e s a m e d e v i c e d o n
AS4C32M16D1A - c&i 19 rev. 1. 0 mar . / 20 1 5 figure 9. non - consecutive read bursts required cas latencies (cl=2) non - consecutive read bursts required cas l atencies (cl=2.5) c k c k c o m m a n d r e a d n o p n o p r e a d n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 d o n t c a r e b a n k , c o l o d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n ( a n d f o l l o w i n g d o o ) d o o d o n c k c k c o m m a n d r e a d n o p n o p r e a d n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e b a n k , c o l o n o p d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n ( a n d f o l l o w i n g d o o ) d o n d o o
AS4C32M16D1A - c&i 20 rev. 1. 0 mar . / 20 1 5 non - consecutive read bursts required cas latencies (cl=3) c k c k c o m m a n d r e a d n o p n o p r e a d n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e b a n k , c o l o n o p d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n ( a n d f o l l o w i n g d o o ) d o o d o n
AS4C32M16D1A - c&i 21 rev. 1. 0 mar . / 20 1 5 figure 10. random read accesses required cas latencies (cl=2) random read accesse s required cas latencies (cl=2.5) d o p d o n ' d o o d o o ' d o p ' d o q c k c k c o m m a n d r e a d r e a d r e a d r e a d n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 d o n t c a r e b a n k , c o l o b a n k , c o l p b a n k , c o l q d o n , e t c . = d a t a o u t f r o m c o l u m n n , e t c . n ' , e t c . = t h e n e x t d a t a o u t f o l l o w i n g d o n , e t c . a c c o r d i n g t o t h e p r o g r a m m e d b u r s t o r d e r b u r s t l e n g t h = 2 , 4 o r 8 i n c a s e s s h o w n . i f b u r s t o f 4 o r 8 , t h e b u r s t i s i n t e r r u p t e d r e a d s a r e t o a c t i v e r o w s i n a n y b a n k s d o n d o p d o n ' d o o d o o ' d o p ' c k c k c o m m a n d r e a d r e a d r e a d r e a d n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e b a n k , c o l o b a n k , c o l p b a n k , c o l q d o n , e t c . = d a t a o u t f r o m c o l u m n n , e t c . n ' , e t c . = t h e n e x t d a t a o u t f o l l o w i n g d o n , e t c . a c c o r d i n g t o t h e p r o g r a m m e d b u r s t o r d e r b u r s t l e n g t h = 2 , 4 o r 8 i n c a s e s s h o w n . i f b u r s t o f 4 o r 8 , t h e b u r s t i s i n t e r r u p t e d r e a d s a r e t o a c t i v e r o w s i n a n y b a n k s d o n
AS4C32M16D1A - c&i 22 rev. 1. 0 mar . / 20 1 5 random read accesses required cas latencies (cl=3) d o p d o n ' d o o d o o ' c k c k c o m m a n d r e a d r e a d r e a d r e a d n o p n o p b a n k , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e b a n k , c o l o b a n k , c o l p b a n k , c o l q d o n , e t c . = d a t a o u t f r o m c o l u m n n , e t c . n ' , e t c . = t h e n e x t d a t a o u t f o l l o w i n g d o n , e t c . a c c o r d i n g t o t h e p r o g r a m m e d b u r s t o r d e r b u r s t l e n g t h = 2 , 4 o r 8 i n c a s e s s h o w n . i f b u r s t o f 4 o r 8 , t h e b u r s t i s i n t e r r u p t e d r e a d s a r e t o a c t i v e r o w s i n a n y b a n k s d o n
AS4C32M16D1A - c&i 23 rev. 1. 0 mar . / 20 1 5 figure 1 1. terminating a read burst required cas latencies (cl=2) terminatin g a read burst required cas latencies (cl=2.5) c k c k c o m m a n d r e a d n o p b s t n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q c l = 2 d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n c a s e s s h o w n a r e b u r s t s o f 8 t e r m i n a t e d a f t e r 4 d a t a e l e m e n t s 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d o n c k c k c o m m a n d r e a d n o p b s t n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n c a s e s s h o w n a r e b u r s t s o f 8 t e r m i n a t e d a f t e r 4 d a t a e l e m e n t s 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d o n
AS4C32M16D1A - c&i 24 rev. 1. 0 mar . / 20 1 5 terminating a read burst required cas latencies (cl=3) c k c k c o m m a n d r e a d n o p b s t n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n c a s e s s h o w n a r e b u r s t s o f 8 t e r m i n a t e d a f t e r 4 d a t a e l e m e n t s 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d o n
AS4C32M16D1A - c&i 25 rev. 1. 0 mar . / 20 1 5 figure 12. read to write required cas latencies (cl=2) r e a d b s t n o p w r i t e n o p n o p b a n k , c o l n c l = 2 d o n t c a r e b a n k , c o l o d i o t d q s s m i n d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 i n t h e c a s e s s h o w n ( a p p l i e s f o r b u r s t s o f 8 a s w e l l ; i f b u r s t l e n g t h i s 2 , t h e b s t c o m m a n d s h o w n c a n b e n o p ) 1 s u b s e q u e n t e l e m e n t o f d a t a o u t a p p e a r s i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d a t a i n e l e m e n t s a r e a p p l i e d f o l l o w i n g d i o i n t h e p r o g r a m m e d o r d e r d o n c k c k c o m m a n d a d d r e s s d q s d q d m
AS4C32M16D1A - c&i 26 rev. 1. 0 mar . / 20 1 5 read to write required cas latencies (cl=2.5) c k c k c o m m a n d r e a d b s t n o p n o p w r i t e n o p b a n k , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e m i n t d q s s d i o d m b a n k , c o l o d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 i n t h e c a s e s s h o w n ( a p p l i e s f o r b u r s t s o f 8 a s w e l l ; i f b u r s t l e n g t h i s 2 , t h e b s t c o m m a n d s h o w n c a n b e n o p ) 1 s u b s e q u e n t e l e m e n t o f d a t a o u t a p p e a r s i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d a t a i n e l e m e n t s a r e a p p l i e d f o l l o w i n g d i o i n t h e p r o g r a m m e d o r d e r d o n
AS4C32M16D1A - c&i 27 rev. 1. 0 mar . / 20 1 5 read to write required cas latencies (cl=3) c k c k c o m m a n d r e a d b s t n o p n o p w r i t e n o p b a n k , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e b a n k , c o l o m i n t d q s s d i o d m d o n ( o r o ) = d a t a o u t f r o m c o l u m n n ( o r c o l u m n o ) b u r s t l e n g t h = 4 i n t h e c a s e s s h o w n ( a p p l i e s f o r b u r s t s o f 8 a s w e l l ; i f b u r s t l e n g t h i s 2 , t h e b s t c o m m a n d s h o w n c a n b e n o p ) 1 s u b s e q u e n t e l e m e n t o f d a t a o u t a p p e a r s i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d a t a i n e l e m e n t s a r e a p p l i e d f o l l o w i n g d i o i n t h e p r o g r a m m e d o r d e r d o n
AS4C32M16D1A - c&i 28 rev. 1. 0 mar . / 20 1 5 figure 13. read to precharge required cas latencies (cl=2) c k c k c o m m a n d r e a d n o p p r e n o p n o p a c t b a n k a , c o l n a d d r e s s d q s d q c l = 2 d o n t c a r e b a n k ( a o r a l l ) b a n k a , r o w t r p d o n = d a t a o u t f r o m c o l u m n n c a s e s s h o w n a r e e i t h e r u n i n t e r r u p t e d b u r s t s o f 4 , o r i n t e r r u p t e d b u r s t s o f 8 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n p r e c h a r g e m a y b e a p p l i e d a t ( b l / 2 ) t c k a f t e r t h e r e a d c o m m a n d n o t e t h a t p r e c h a r g e m a y n o t b e i s s u e d b e f o r e t r a s n s a f t e r t h e a c t i v e c o m m a n d f o r a p p l i c a b l e b a n k s t h e a c t i v e c o m m a n d m a y b e a p p l i e d i f t r c h a s b e e n m e t d o n
AS4C32M16D1A - c&i 29 rev. 1. 0 mar . / 20 1 5 read to precharge required cas latencies (cl=2.5) c k c k c o m m a n d r e a d n o p p r e n o p n o p a c t b a n k a , c o l n a d d r e s s d q s d q c l = 2 . 5 d o n t c a r e b a n k ( a o r a l l ) b a n k a , r o w t r p d o n = d a t a o u t f r o m c o l u m n n c a s e s s h o w n a r e e i t h e r u n i n t e r r u p t e d b u r s t s o f 4 , o r i n t e r r u p t e d b u r s t s o f 8 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n p r e c h a r g e m a y b e a p p l i e d a t ( b l / 2 ) t c k a f t e r t h e r e a d c o m m a n d n o t e t h a t p r e c h a r g e m a y n o t b e i s s u e d b e f o r e t r a s n s a f t e r t h e a c t i v e c o m m a n d f o r a p p l i c a b l e b a n k s t h e a c t i v e c o m m a n d m a y b e a p p l i e d i f t r c h a s b e e n m e t d o n
AS4C32M16D1A - c&i 30 rev. 1. 0 mar . / 20 1 5 read to precharge required cas latencies (cl=3) c k c k c o m m a n d r e a d n o p p r e n o p n o p a c t b a n k a , c o l n a d d r e s s d q s d q c l = 3 d o n t c a r e b a n k ( a o r a l l ) b a n k a , r o w t r p d o n = d a t a o u t f r o m c o l u m n n c a s e s s h o w n a r e e i t h e r u n i n t e r r u p t e d b u r s t s o f 4 , o r i n t e r r u p t e d b u r s t s o f 8 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a p p e a r i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n p r e c h a r g e m a y b e a p p l i e d a t ( b l / 2 ) t c k a f t e r t h e r e a d c o m m a n d n o t e t h a t p r e c h a r g e m a y n o t b e i s s u e d b e f o r e t r a s n s a f t e r t h e a c t i v e c o m m a n d f o r a p p l i c a b l e b a n k s t h e a c t i v e c o m m a n d m a y b e a p p l i e d i f t r c h a s b e e n m e t d o n
AS4C32M16D1A - c&i 31 rev. 1. 0 mar . / 20 1 5 figure 14. write command c k c k c k e c s r a s c a s w e c a a 0 - a 9 a 1 0 d o n t c a r e h i g h e n a p d i s a p b a b a 0 , 1 c a = c o l u m n a d d r e s s b a = b a n k a d d r e s s e n a p = e n a b l e a u t o p r e c h a r g e d i s a p = d i s a b l e a u t o p r e c h a r g e
AS4C32M16D1A - c&i 32 rev. 1. 0 mar . / 20 1 5 figure 15. write max dqss c k c k c o m m a n d w r i t e n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q t d q s s d o n t c a r e d m t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 m a x d i n d i n = d a t a i n f o r c o l u m n n 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n a n o n - i n t e r r u p t e d b u r s t o f 4 i s s h o w n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e d i s a b l e d )
AS4C32M16D1A - c&i 33 rev. 1. 0 mar . / 20 1 5 figure 16. write min dqss c k c k c o m m a n d w r i t e n o p n o p n o p b a n k a , c o l n a d d r e s s d q s d q t d q s s d m t 0 t 1 t 2 t 3 t 4 t 5 t 6 m i n d i n d o n t c a r e d i n = d a t a i n f o r c o l u m n n 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n a n o n - i n t e r r u p t e d b u r s t o f 4 i s s h o w n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e d i s a b l e d )
AS4C32M16D1A - c&i 34 rev. 1. 0 mar . / 20 1 5 figure 17. write burst nom, min, and max tdqss c k c k c o m m a n d w r i t e n o p n o p n o p b a n k , c o l n a d d r e s s d q s d q t d q s s ( n o m ) d o n t c a r e d m t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 d i n t 8 t 9 t 1 0 t 1 1 n o p n o p d q s d q t d q s s ( m i n ) d m d i n d q s d q t d q s s ( m a x ) d m d i n d i n = d a t a i n f o r c o l u m n n 3 s u b s e q u e n t e l e m e n t s o f d a t a a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n a n o n - i n t e r r u p t e d b u r s t o f 4 i s s h o w n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e d i s a b l e d ) d m = u d m & l d m
AS4C32M16D1A - c&i 35 rev. 1. 0 mar . / 20 1 5 figure 18. write to write max tdqss c k c k c o m m a n d w r i t e n o p w r i t e n o p b a n k , c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 n o p n o p d q s d q t d q s s ( m a x ) d m d i n b a n k , c o l o d i o d o n t c a r e d i n , e t c . = d a t a i n f o r c o l u m n n , e t c . 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n n o n - i n t e r r u p t e d b u r s t s o f 4 a r e s h o w n d m = u d m & l d m 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i o
AS4C32M16D1A - c&i 36 rev. 1. 0 mar . / 20 1 5 figure 19. write to write max tdqss, non consecutive c k c k c o m m a n d w r i t e n o p n o p w r i t e b a n k c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 t 1 1 n o p n o p d q s d q t d q s s ( m a x ) d m d i n b a n k c o l o d i o d o n t c a r e d i n , e t c . = d a t a i n f o r c o l u m n n , e t c . 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n n o n - i n t e r r u p t e d b u r s t s o f 4 a r e s h o w n d m = u d m & l d m 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i o
AS4C32M16D1A - c&i 37 rev. 1. 0 mar . / 20 1 5 figure 20. random write cycles max tdqss c k c k c o m m a n d w r i t e w r i t e w r i t e w r i t e b a n k c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 w r i t e d q s d q t d q s s ( m a x ) d m d i n b a n k c o l q d i o d i n ' d i o ' d i p d i p ' d i q d i q ' b a n k c o l o b a n k c o l p b a n k c o l r d o n t c a r e d i n , e t c . = d a t a i n f o r c o l u m n n , e t c . n ' , e t c . = t h e n e x t d a t a i n f o l l o w i n g d i n , e t c . a c c o r d i n g t o t h e p r o g r a m m e d b u r s t o r d e r i f b u r s t o f 4 o r 8 , t h e b u r s t w o u l d b e t r u n c a t e d d m = u d m & l d m p r o g r a m m e d b u r s t l e n g t h 2 , 4 , o r 8 i n c a s e s s h o w n e a c h w r i t e c o m m a n d m a y b e t o a n y b a n k a n d m a y b e t o t h e s a m e o r d i f f e r e n t d e v i c e s
AS4C32M16D1A - c&i 38 rev. 1. 0 mar . / 20 1 5 figure 21. write to read max tdqss non interrup ting c k c k c o m m a n d w r i t e n o p n o p r e a d b a n k c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 n o p d q s d q t d q s s ( m a x ) d m d i n b a n k c o l o t 1 0 t 1 1 n o p t w t r c l = 3 d o n t c a r e d i n , e t c . = d a t a i n f o r c o l u m n n , e t c . 1 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n t w t r i s r e f e r e n c e d f r o m t h e f i r s t p o s i t i v e c k e d g e a f t e r t h e l a s t d a t a i n p a i r d m = u d m & l d m a n o n - i n t e r r u p t e d b u r s t o f 2 i s s h o w n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) t h e r e a d a n d w r i t e c o m m a n d s a r e t o t h e s a m e d e v i c e s b u t n o t n e c e s s a r i l y t o t h e s a m e b a n k t 1 2 n o p
AS4C32M16D1A - c&i 39 rev. 1. 0 mar . / 20 1 5 figure 22. write to read max tdqss interrupting c k c k c o m m a n d w r i t e n o p n o p r e a d b a n k c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 n o p d q s d q t d q s s ( m a x ) d m d i n b a n k c o l o t 1 0 t 1 1 n o p t w t r c l = 3 d o n t c a r e d i n , e t c . = d a t a i n f o r c o l u m n n , e t c . 1 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n t w t r i s r e f e r e n c e d f r o m t h e f i r s t p o s i t i v e c k e d g e a f t e r t h e l a s t d a t a i n p a i r d m = u d m & l d m a n i n t e r r u p t e d b u r s t o f 8 i s s h o w n , 2 d a t a e l e m e n t s a r e w r i t t e n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) t h e r e a d a n d w r i t e c o m m a n d s a r e t o t h e s a m e d e v i c e s b u t n o t n e c e s s a r i l y t o t h e s a m e b a n k t 1 2
AS4C32M16D1A - c&i 40 rev. 1. 0 mar . / 20 1 5 figure 23. write to read max tdqss, odd number of data, interrupting c k c k w r i t e n o p n o p r e a d b a n k c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 n o p d q s d q t d q s s ( m a x ) d m d i n b a n k c o l o t 1 0 t 1 1 n o p t w t r c l = 3 d o n t c a r e d i n = d a t a i n f o r c o l u m n n t w t r i s r e f e r e n c e d f r o m t h e f i r s t p o s i t i v e c k e d g e a f t e r t h e l a s t d a t a i n p a i r ( n o t t h e l a s t d e s i r e d d a t a i n e l e m e n t ) d m = l d m & u d m a n i n t e r r u p t e d b u r s t o f 8 i s s h o w n , 1 d a t a e l e m e n t s a r e w r i t t e n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) t h e r e a d a n d w r i t e c o m m a n d s a r e t o t h e s a m e d e v i c e s b u t n o t n e c e s s a r i l y t o t h e s a m e b a n k t 1 2 c o m m a n d
AS4C32M16D1A - c&i 41 rev. 1. 0 mar . / 20 1 5 figure 24. write to precharge max tdqss , non - interrupting c k c k c o m m a n d w r i t e n o p n o p n o p b a n k a , c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 p r e d q s d q t d q s s ( m a x ) d m d i n b a n k ( a o r a l ) t 1 0 t 1 1 n o p t w r t r p d o n t c a r e d i n = d a t a i n f o r c o l u m n n 1 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n t w r i s r e f e r e n c e d f r o m t h e f i r s t p o s i t i v e c k e d g e a f t e r t h e l a s t d a t a i n p a i r d m = u d m & l d m a n o n - i n t e r r u p t e d b u r s t o f 2 i s s h o w n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d )
AS4C32M16D1A - c&i 42 rev. 1. 0 mar . / 20 1 5 figure 25. write to precharge max tdqss, interrupting c k c k c o m m a n d w r i t e n o p n o p p r e b a n k a , c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 n o p d q s d q t d q s s ( m a x ) d m d i n t 1 0 t 1 1 n o p t w r t r p * 1 * 2 d o n t c a r e d i n = d a t a i n f o r c o l u m n n t w r i s r e f e r e n c e d f r o m t h e f i r s t p o s i t i v e c k e d g e a f t e r t h e l a s t d a t a i n p a i r d m = u d m & l d m a n i n t e r r u p t e d b u r s t o f 4 o r 8 i s s h o w n , 2 d a t a e l e m e n t s a r e w r i t t e n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) * 1 = c a n b e d o n ' t c a r e f o r p r o g r a m m e d b u r s t l e n g t h o f 4 * 2 = f o r p r o g r a m m e d b u r s t l e n g t h o f 4 , d q s b e c o m e s d o n ' t c a r e a t t h i s p o i n t * 1 * 1 * 1 b a n k ( a o r a l l )
AS4C32M16D1A - c&i 43 rev. 1. 0 mar . / 20 1 5 figure 26. write to precharge max tdqss odd number of data interrupting c k c k c o m m a n d w r i t e n o p n o p b a n k a , c o l n a d d r e s s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 n o p d q s d q t d q s s ( m a x ) d m d i n t 1 0 t 1 1 n o p t w r t r p * 2 d o n t c a r e d i n = d a t a i n f o r c o l u m n n t w r i s r e f e r e n c e d f r o m t h e f i r s t p o s i t i v e c k e d g e a f t e r t h e l a s t d a t a i n p a i r d m = u d m & l d m a n i n t e r r u p t e d b u r s t o f 4 o r 8 i s s h o w n , 1 d a t a e l e m e n t i s w r i t t e n a 1 0 i s l o w w i t h t h e w r i t e c o m m a n d ( a u t o p r e c h a r g e i s d i s a b l e d ) * 1 = c a n b e d o n ' t c a r e f o r p r o g r a m m e d b u r s t l e n g t h o f 4 * 2 = f o r p r o g r a m m e d b u r s t l e n g t h o f 4 , d q s b e c o m e s d o n ' t c a r e a t t h i s p o i n t * 1 * 1 * 1 * 1 p r e b a n k ( a o r a l l )
AS4C32M16D1A - c&i 44 rev. 1. 0 mar . / 20 1 5 figure 27 . prec harge command c k c k c k e c s r a s c a s w e a 0 - a 9 , a 1 1 , a 1 2 a 1 0 d o n t c a r e h i g h a l l b a n k s o n e b a n k b a b a 0 , 1 b a = b a n k a d d r e s s ( i f a 1 0 i s l o w , o t h e r w i s e d o n ' t c a r e )
AS4C32M16D1A - c&i 45 rev. 1. 0 mar . / 20 1 5 figure 28. p ower - down figure 29. clock frequency change in precharge c k c k c k e v a l i d c o m m a n d d o n t c a r e t 0 t 1 t 2 t 3 t 4 t n t n + 1 t n + 2 t n + 3 t n + 4 v a l i d t n + 5 t n + 6 n o p n o p n o c o l u m n a c c e s s i n p r o g r e s s e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t i s t i s c k c k c m d t i s t 0 t 1 t 2 t 4 t x t x + 1 t y t y + 1 t y + 2 t y + 3 t y + 4 t z n o p n o p n o p d l l r e s e t n o p v a l i d n o p f r e q u e n c y c h a n g e o c c u r s h e r e s t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t t r p m i n m u m 2 c l o c k s r e q u i r e d b e f o r e c h a n g i n g f r e q u e n c y 2 0 0 c l o c k s c k e
AS4C32M16D1A - c&i 46 rev. 1. 0 mar . / 20 1 5 figure 30. data input (write) timing figure 31. data output (read) timing d q s d q d o n t c a r e t d s d i n d m t d h t d s t d h t d q s h t d q s l d i n = d a t a i n f o r c o l u m n n b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e a p p l i e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n c k c k d q t c h t c l t q h t d q s q m a x t q h m a x t d q s q b u r s t l e n g t h = 4 i n t h e c a s e s h o w n d q s
AS4C32M16D1A - c&i 47 rev. 1. 0 mar . / 20 1 5 figure 32. initialize and mode register sets t i s t i h n o p p r e e m r s m r s p r e a r a r m r s a c t c o d e c o d e c o d e r a t v d t > = 0 t c h t c l t c k t i s t i h t i s t i h c o d e c o d e c o d e r a t i s t i h t i s t i h a l l b a n k s t i s t i h a l l b a n k s b a 0 = h b a 1 = l b a 0 = l b a 1 = l b a 0 = l b a 1 = l b a t i s t i h h i g h - z h i g h - z l v c m o s l o w l e v e l c k c k d m a 0 - a 9 , a 1 1 , a 1 2 c o m m a n d v r e f c k e a 1 0 b a 0 , b a 1 d q s d q v d d v d d q v t t ( s y s t e m * ) * = v t t i s n o t a p p l i e d d i r e c t l y t o t h e d e v i c e , h o w e v e r t v t d m u s t b e g r e a t e r t h a n o r e q u a l t o z e r o t o a v o i d d e v i c e l a t c h - u p . * * = t m r d i s r e q u i r e d b e f o r e a n y c o m m a n d c a n b e a p p l i e d , a n d 2 0 0 c y c l e s o f c k a r e r e q u i r e d b e f o r e a n y e x e c u t a b l e c o m m a n d c a n b e a p p l i e d t h e t w o a u t o r e f r e s h c o m m a n d s m a y b e m o v e d t o f o l l o w t h e f i r s t m r s b u t p r e c e d e t h e s e c o n d p r e c h a r g e a l l c o m m a n d . d o n t c a r e p o w e r - u p : v d d a n d c l k s t a b l e e x t e n d e d m o d e r e g i s t e r s e t l o a d m o d e r e g i s t e r , r e s e t d l l ( w i t h a 8 = h ) 2 0 0 c y c l e s o f c k * * l o a d m o d e r e g i s t e r , ( w i t h a 8 = l ) t = 2 0 0 s * * t m r d * * t m r d t r f c t r f c * * t m r d t r p
AS4C32M16D1A - c&i 48 rev. 1. 0 mar . / 20 1 5 figure 33 . power down mode c k c k c k e v a l i d * c o m m a n d d o n t c a r e v a l i d t c k n o p n o p e n t e r p o w e r - d o w n m o d e e x i t p o w e r - d o w n m o d e t c h t c l t i s t i s t i h t i s t i s t i h v a l i d t i s t i h a d d r v a l i d d q s d q d m n o c o l u m n a c c e s s e s a r e a l l o w e d t o b e i n p r o g r e s s a t t h e t i m e p o w e r - d o w n i s e n t e r e d * = i f t h i s c o m m a n d i s a p r e c h a r g e a l l ( o r i f t h e d e v i c e i s a l r e a d y i n t h e i d l e s t a t e ) t h e n t h e p o w e r - d o w n m o d e s h o w n i s p r e c h a r g e p o w e r d o w n . i f t h i s c o m m a n d i s a n a c t i v e ( o r i f a t l e a s t o n e r o w i s a l r e a d y a c t i v e ) t h e n t h e p o w e r - d o w n m o d e s h o w n i s a c t i v e p o w e r d o w n .
AS4C32M16D1A - c&i 4 9 rev. 1. 0 mar . / 20 1 5 figure 34. auto refresh mod e c k c k a 0 - a 9 a 1 1 , a 1 2 v a l i d n o p t i s d o n t c a r e t i h n o p a r n o p a r n o p n o p a c t t i s t i h t c h t c l t c k r a c k e r a a 1 0 b a 0 , b a 1 d q s d q * b a n k ( s ) v a l i d n o p p r e r a a l l b a n k s o n e b a n k s b a t i h t i s d m t r p t r f c t r f c * =
AS4C32M16D1A - c&i 50 rev. 1. 0 mar . / 20 1 5 figure 35. self refresh mode c k c k c k e n o p c o m m a n d d o n t c a r e v a l i d t c k a r n o p c l o c k m u s t b e s t a b l e b e f o r e e x i t i n g s e l f r e f r e s h m o d e e n t e r s e l f r e f r e s h m o d e t c h t c l t i s t i s t i h t i s t i s t i h a d d r v a l i d d q s d q d m t i s t i h t r p * t x s n r / t x s r d * * e x i t s e l f r e f r e s h m o d e * = d e v i c e m u s t b e i n t h e
AS4C32M16D1A - c&i 51 rev. 1. 0 mar . / 20 1 5 figure 36. read without auto precharge c k c k a 0 - a 9 n o p t i s t i h p r e n o p n o p v a l i d v a l i d v a l i d t i s t i h t c h t c l t c k r a c k e d m d q s n o p r e a d r a t i h t i s d q c l = 3 t r p a c t n o p n o p n o p c o l n t i s t i h r a a l l b a n k s o n e b a n k s b a n k x t i s t i h d i s a p * b a n k x b a n k x t r p r e t d q s c k m i n t r p s t t l z t l z t a c m i n d q s d q t r p r e t r p s t t l z t l z m a x t d q s c k t h z m a x t i h m a x m a x m i n m i n d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n p r e = p r e c h a r g e , a c t = a c t i v e , r a = r o w a d d r e s s , b a = b a n k a d d r e s s , a r = a u t o r e f r e s h b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d i s a p = d i s a b l e a u t o p r e c h a r g e * = t a c c a s e 1 : t a c / t d q s c k = m i n c a s e 2 : t a c / t d q s c k = m a x
AS4C32M16D1A - c&i 52 rev. 1. 0 mar . / 20 1 5 figure 37. read with auto precharge n o p t i s t i h n o p n o p n o p v a l i d v a l i d v a l i d t i s t i h t c h t c l t c k r a n o p r e a d r a t i h t i s c l = 3 t r p a c t n o p n o p n o p c o l n t i s t i h r a b a n k x t i s t i h e n a p b a n k x t r p r e m i n t r p s t t l z t a c m i n t r p r e t r p s t t l z t l z m a x t d q s c k t h z m a x t i h m i n m a x m a x d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n e n a p = e n a b l e a u t o p r e c h a r g e a c t = a c t i v e , r a = r o w a d d r e s s n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s t h e r e a d c o m m a n d m a y n o t b e i s s u e d u n t i l t r a p h a s b e e n s a t i s f i e d . i f f a s t a u t o p r e c h a r g e i s s u p p o r t e d , t r a p = t r c d , e l s e t h e r e a d m a y n o t b e i s s u e d p r i o r t o t r a s m i n C t a c m i n t l z t d q s c k c k c k a 0 - a 9 c o m m a n d c k e a 1 0 b a 0 , b a 1 d m d q s d q d q s d q a 1 1 , a 1 2 c a s e 2 : t a c / t d q s c k = m a x c a s e 1 : t a c / t d q s c k = m i n
AS4C32M16D1A - c&i 53 rev. 1. 0 mar . / 20 1 5 figure 38. bank read ac cess n o p t i s t i h n o p n o p r e a d t i s t i h t c h t c l t c k n o p a c t r a t i h t i s t r c n o p p r e n o p n o p r a t i s t i h c o l n a l l b a n k s o n e b a n k s d i s a p b a n k x t r p r e m i n t r p s t t l z t l z t a c a c t r a r a r a r a * b a n k x b a n k x t i s t i h b a n k x t r a s t r c d t r p t d q s c k m i n m i n t r p r e m a x t l z t a c m a x m a x t r p s t t d q s c k d o n t c a r e d o n = d a t a o u t f r o m c o l u m n n p r e = p r e c h a r g e , a c t = a c t i v e , r a = r o w a d d r e s s , b a = b a n k a d d r e s s b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d o n d i s a p = d i s a b l e a u t o p r e c h a r g e * = t l z m a x t h z d q d q s c a s e 2 : t a c / t d q s c k = m a x d q d q s c a s e 1 : t a c / t d q s c k = m i n d m b a 0 , b a 1 c o m m a n d c k e c k c k a 1 0 a 1 1 , a 1 2 a 0 - a 9
AS4C32M16D1A - c&i 54 rev. 1. 0 mar . / 20 1 5 figure 39. write without auto precharge c k c k a 0 - a 9 a 1 1 , a 1 2 n o p c o m m a n d t i s t i h n o p n o p n o p v a l i d t i s t i h t c h t c l t c k r a c k e a 1 0 b a 0 , b a 1 d q s n o p w r i t e r a t i h t i s d q t d s h p r e n o p n o p a c t c o l n t i s t i h r a a l l b a n k s o n e b a n k s b a n k x t i s t i h d i s a p * b a n k x b a t w p r e s c a s e 1 : t d q s s = m i n d i n t i h t d q s s t d s h t d q s h t d q s l t w p s t t w p r e d m d q s d q t d s s t w p r e s c a s e 2 : t d q s s = m a x d i n t d q s s t d s s d m t w r t r p t d q s h t w p s t t d q s l t w p r e d o n t c a r e d i n = d a t a i n f r o m c o l u m n n p r e = p r e c h a r g e , a c t = a c t i v e , r a = r o w a d d r e s s , b a = b a n k a d d r e s s , a r = a u t o r e f r e s h b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n d i s a p = d i s a b l e a u t o p r e c h a r g e * =
AS4C32M16D1A - c&i 55 rev. 1. 0 mar . / 20 1 5 figure 40. write with auto prechar ge c k c k a 0 - a 9 a 1 1 , a 1 2 n o p c o m m a n d t i s t i h n o p n o p n o p v a l i d t i s t i h t c h t c l t c k r a c k e a 1 0 b a 0 , b a 1 d q s n o p w r i t e r a t i h t i s d q t d s h n o p n o p n o p a c t c o l n t i s t i h r a b a n k x d i s a p b a t w p r e s c a s e 1 : t d q s s = m i n d i n t d q s s t d s h t d q s h t d q s l t w p s t t w p r e d m d q s d q t d s s t w p r e s c a s e 2 : t d q s s = m a x d i n t d q s s t d s s d m t d a l t d q s h t w p s t t d q s l v a l i d v a l i d t w p r e d o n t c a r e d i n = d a t a i n f r o m c o l u m n n b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n e n a p = e n a b l e a u t o p r e c h a r g e a c t = a c t i v e , r a = r o w a d d r e s s , b a = b a n k a d d r e s s n o p c o m m a n d s a r e s h o w n f o r e a s e o f i l l u s t r a t i o n ; o t h e r c o m m a n d s m a y b e v a l i d a t t h e s e t i m e s a l t h o u g h t d q s s i s d r a w n o n l y f o r t h e f i r s t d q s r i s i n g e d g e , e a c h r i s i n g e d g e o f d q s m u s t f a l l w i t h i n t h e + 2 5 % w i n d o w o f t h e c o r r e s p o n d i n g p o s i t i v e c l o c k e d g e
AS4C32M16D1A - c&i 56 rev. 1. 0 mar . / 20 1 5 figure 41. bank write access c k c k a 0 - a 9 a 1 1 , a 1 2 n o p c o m m a n d t i s t i h n o p w r i t e n o p t i s t i h t c h t c l t c k c k e a 1 0 b a 0 , b a 1 d q s n o p a c t a l l b a n k s t i h t i s d q t d s h n o p n o p n o p p r e r a t i s t i h b a n k x d i s a p * b a n k x t w p r e s c a s e 1 : t d q s s = m i n d i n t d q s s t d s h t d q s h t d q s l t w p s t d m d q s d q c a s e 2 : t d q s s = m a x t d q s s t d s s d m t r a s t d q s h t w p s t c o l n r a r a o n e b a n k t i s t i h b a n k x t w r t r c d t w p r e t d s s t d q s l t w p r e s t w p r e d i n d o n t c a r e d i n = d a t a i n f r o m c o l u m n n p r e = p r e c h a r g e , a c t = a c t i v e , r a = r o w a d d r e s s , b a = b a n k a d d r e s s b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a o u t a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n d i s a p = d i s a b l e a u t o p r e c h a r g e * =
AS4C32M16D1A - c&i 57 rev. 1. 0 mar . / 20 1 5 figure 42. write dm operation c k c k a 0 - a 9 a 1 1 , a 1 2 n o p c o m m a n d t i s t i h n o p n o p n o p v a l i d t i s t i h t c h t c l t c k r a c k e a 1 0 b a 0 , b a 1 d q s n o p w r i t e r a t i h t i s d q t d s h p r e n o p n o p a c t c o l n t i s t i h r a a l l b a n k s o n e b a n k s b a n k x t i s t i h d i s a p * b a n k x b a t w p r e s c a s e 1 : t d q s s = m i n d i n t d q s s t d s h t d q s h t d q s l t w p s t t w p r e d m d q s d q t d s s t w p r e s c a s e 2 : t d q s s = m a x d i n t d q s s t d s s d m t w r t r p t d q s h t d q s l t w p r e t w p s t d o n t c a r e d i n = d a t a i n f r o m c o l u m n n p r e = p r e c h a r g e , a c t = a c t i v e , r a = r o w a d d r e s s , b a = b a n k a d d r e s s b u r s t l e n g t h = 4 i n t h e c a s e s h o w n 3 s u b s e q u e n t e l e m e n t s o f d a t a i n a r e p r o v i d e d i n t h e p r o g r a m m e d o r d e r f o l l o w i n g d i n d i s a p = d i s a b l e a u t o p r e c h a r g e * =
AS4C32M16D1A - c&i 58 rev. 1. 0 mar . / 20 1 5 figure 43. 66 pin tsop ii package outline drawing information units: mm symbol dimension in mm dimension in inch min nom max min nom max a --- --- 1.2 --- --- 0.047 a1 0.05 --- 0.2 0.002 --- 0.008 a2 0.9 1.0 1.1 0.035 0.039 0.043 b 0.22 --- 0.45 0.009 --- 0.018 e --- 0.65 --- --- 0.026 --- c 0.095 0.125 0.21 0.004 0.005 0.008 d 22.09 22.22 22.35 0.87 0.875 0.88 e 10.03 10.16 10.29 0.395 0.4 0.405 he 11.56 11.76 11.96 0.455 0.463 0.471 l 0.40 0.5 0.6 0.016 0.02 0.024 l1 --- 0.8 --- --- 0.032 --- f --- 0.25 --- --- 0.01 --- 0 --- 8 0 --- 8 s --- 0.71 --- --- 0.028 --- --- --- 0.10 --- --- 0.004 d y d c s b d f (typ) c e a a1 a2 e he l1 l
AS4C32M16D1A - c&i 59 rev. 1. 0 mar . / 20 1 5 part numbering system as4c 32 m16 d1a 5 t c/i n dram 32 m16= 32 mx16 bit d1a = ddr1 a version 5 = 200 mhz t = tsop ii c=commercial ( 0 c 70 c) i=industrial ( - 40 c 8 5 c) indicates pb and halogen free alliance memory, inc. 511 taylor way, san carlos, ca 94070 tel: 650 - 610 - 6800 fax: 650 - 620 - 9211 www.alliancememory.com copyright ? alliance memory all rights reserv ed ? copyright 200 7 alliance memory, inc. all rights reserved. our three - point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. al liance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or est imates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liabil ity arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, me rchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance's term s and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authori ze its products for use as critical components in life - supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life - supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use.

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